1. Field of the Invention
The present invention relates to a local bus bridge and, in particular, the present invention relates to a local bus bridge for dividing a serial bus into first and second local buses to mutually send/receive information between nodes connected to the local buses.
2. Description of Related Art
There has been recent tendency for the performance of computers to become higher and higher, and peripheral devices such as memory devices thereof are advanced correspondingly. Historically, electric or electronic products for home use have been clearly distinguished from computerized products. However, the computerization of home use products and the digitalization of home use products have advanced, so that an environment, in which both can co-exist has become necessary.
Under such background, as an interface capable of realizing a high speed transfer of a large amount of data, there is a high speed serial bus standardized by IEEE (The Institute of Electrical and Electronics Engineers) 1394. The high speed serial bus will be referred to as IEEE1394 bus, hereinafter. The IEEE1394 bus is described in “IEEE Standard for a High Performance Serial Bus”, which will be referred to as IEEE1394-1995, hereinafter.
In the IEEE1394-1995, the data transfer speed is defined as 100 Mbps, 200 Mbps and 400 Mbps. Further, in IEEE1394.b, which is an expanded standard of the IEEE1394-1995, the maximum data transfer speed is defined as 3200 Mbps.
A signal line is constructed with shielded twisted pairs and is driven by a small amplitude differential signal by taking anti noise characteristics thereof into consideration. Data is constructed with a data portion and a strobe portion, and a clock signal is generated on a receiving side by an exclusive OR of the data portion and the strobe portion.
An example of a network constructed by using the IEEE1394 bus is shown in FIG. 38. The IEEE1394 bus employs a cable 2100, which can be easily handled and has a simple construction. Further, the connection configuration is not limited to the daisy chain connection such as nodes (terminal devices) 2101 to 210n as in the SCSI (Small Computer System Interface). It is possible to connect the node 2101 through nodes 2111, 2121 and 2122 to other nodes 2131 to 2134 by branching the connection at nodes each having a plurality of ports 2130.
An important feature of the IEEE1394 bus is that an addition of a new node to or deletion of a node from a network of the IEEE1394 bus can be done without turning a power source off. In the IEEE1394-1995, the 64-bit fixed addressing according to the IEEE1212 standard is employed.
FIG. 39 shows an address map of the IEEE1394. The most significant 16 bits of each address indicate a node ID 2201. The most significant 10 bits of the node ID 2201 define a bus ID 2202, and the least significant 6 bits thereof define a PHY (Physical) ID 2203. The bus ID 2201 can assign any one of buses numbered “0” to “1023”. The bus number “1023” indicates a local bus 2204, which is directly connected to a node from which data is transferred. The PHY ID 2203 can assign any one of nodes number “0” to “63”. The node number “63” indicates broadcast 2205, by which data should be transferred to all nodes connected to the bus.
Therefore, in the IEEE1394, the number of buses is 1023 and 63 nodes can be connected to each bus. Consequently, a total of 64449 nodes can be connected by the IEEE1394 bus. An address space assigned to each node includes the remaining 48 bits (256 terabytes). Addresses from 0 to ‘FFFF DFFF FFFF’ are assigned to a memory space 2208, addresses from ‘FFFF E000 0000’ to ‘FFFF FFFF FFFF’ are assigned to a private space 2207 and addresses from ‘FFFF F000 0000’ to ‘FFFF FFFF FFFF’ are assigned to a register space 2206, where the numbers marked off by inverted commas are hexadecimal numbers.
The register of the IEEE1394 is defined by a style employing CSR (Control and Status Registers) architecture standardized by the IEEE1212. Addresses from ‘000 0000’ to ‘000 01FF’ of the register space of the CSR is constructed with a CSR core and basic register space 2209. Subsequent thereto, addresses from ‘000 0200’ to ‘000 03FF’ is reserved by a bus-dependent service 2210. Further, a space subsequent to the address ‘000 0800’ is reserved as a space 2212 for node-dependent resource in initial units.
A transaction correspondent node has to be installed an information indicative of features and functions of the node, such as company identifier, etc., in a configuration ROM space 2211. The configuration ROM has a minimum format system containing only company identifier such as shown in FIG. 40 or a general format system such as shown in FIG. 41. There are a node vendor ID 2302 (that is, company identifier) and a chip ID 2303 in a bus info block 2301 of the general format.
In FIG. 38, the respective nodes are connected to each other by the cables 2100 each including two sets of twisted pair lines. The port 2130 of each node applies a predetermined bias voltage to a signal line of each cable 2100. When a new node is added to or a node is deleted from the network shown in FIG. 38, for example, when a port 2140 of a node 2141 and the port 2130 of the node 2134 are newly connected to each other by a cable, the node 2134, which detects a variation of the bias voltage on the signal line at the port 2130, sends a bus reset signal, which is a signal for initializing the whole network, to the whole network.
The respective nodes, which receive the bus reset signal, and the node 2134, which transmitted the bus reset signal, annul presently stored buses and presently stored information (topology information) related to the nodes in the network. With this procedure, the initialization of the network is completed. Subsequent thereto, a reconstruction of the topology information is performed in the network.
In this reconstruction of topology information, the PHY ID 2203 shown in FIG. 39 is assigned to each node and a root node for managing a control right of the buses and an isochronous resource manager (referred to as IRM, hereinafter) for managing an isochronous resource to be described later are determined. Since the procedures from the bus initialization to the reconstruction of topology are automatically performed among the respective nodes, a user of the network is not requested to set them for every node. The function of the IEEE1394 bus having these features is not limited to means for providing connection between a computer and peripheral devices thereof. The IEEE1394 bus also makes connections between all devices in homes possible.
On the IEEE1394 bus, a process for transferring packets is referred to as a subaction, which is roughly classified to two kinds. One of the kinds is called as an isochronous subaction having a function of transferring packets at regular intervals, which is the feature of the IEEE1394 bus. In this subaction, the packets are transferred not to a specific node but to all nodes of the whole network by using channel addresses.
The other kind is called as an asynchronous subaction, which is an asynchronous transfer method. Unlike the isochronous subaction, packets can not be transferred at regular intervals in the asynchronous subaction. Instead, a header information of several bytes and a real data are transferred to an assigned node and the assigned node, which received the header information and the real data, returns an acknowledge packet necessarily. However, in a case of a subaction, which does not require acknowledge packet, such as broadcast in which the PHY ID 2203 within a destination address is 63 or an asynchronous stream packet defined in IEEE1394a-2000, which is an expansion standard of the IEEE1394-1995, no acknowledge packet is returned.
An example of a system construction of the IEEE1394 is shown in FIG. 42. A transaction-correspondent node connected to the IEEE1394 bus has a hardware function 2401 composed of a Physical Layer function 2403 and a link layer function 2404 and a firmware function 2402 composed of a transaction layer function 2405 and a serial bus management function 2406. Transmission packets are transmitted from the transaction layer function 2405 through the link layer function 2404 and the physical layer function 2405 to the IEEE1394 bus 2400. Receiving packets are transmitted from the IEEE1394 bus 2400 through the physical layer function 2403 and the link layer function 2404 to the transaction layer function 2405.
The physical layer function 2403 performs a flow from the initialization by bus reset to the construction of topology, a conversion of the serial bus of the IEEE1394 bus 2400 and the parallel bus of the link layer function 2404 and an entry to an arbitration on the IEEE1394 bus 2400, etc. In the topology construction phase, the physical layer function 2403 is to automatically transmit a packet, which is called self identification (self-ID) packet, for notifying other nodes of its node ID 2201, its transfer speed and connection information, etc.
The link layer function 2404 performs a control of a cycle start packet to be described later, a packet transmission control, a retry control, a packet receiving control and the above mentioned CSR management, etc. The transaction layer function 2405 performs a transmission packet generation and a receiving packet processing, etc. The serial bus management function 2406 performs a node control and the above-mentioned IRM function, etc.
An example of a bus on which the isochronous subaction and the asynchronous subaction are performed is shown in FIG. 43. As mentioned above, a root node is settled on the IEEE1394 bus by the topology construction after the bus setting and, in an environment in which there is the isochronous packet, the root node thus settled becomes a cycle master for transmitting a cycle start packet 2502.
The cycle master transmits cycle start packets 2502 at intervals of about 125 μs. When a node, which acquired the isochronous resource from the IRM, detects the cycle start packet 2502, the node transmits an isochronous packet 2503. When the node completes a transfer of all isochronous packets 2503 within the cycle period 2501 of about 125 μs and detects a subaction gap 2506, respective nodes transmit the asynchronous packet 2504 and nodes, which receive the asynchronous packet, return the acknowledge packets 2505 thereto.
Incidentally, the cycle start packet 2502 is also an asynchronous packet. There are two kinds of the transaction in the asynchronous subaction.
FIG. 44 shows a data flow in a unified transaction, which. is one of the two kinds of transaction. In FIG. 44, a request packet transmitted from a transaction layer 2601 of a requesting node is received by a transaction layer 2604 of a response node through a link layer 2602 of the requesting node and a link layer 2603 of the response node. The transaction layer 2604 of the response node immediately transmits an acknowledge packet of completion to the request packet and the transaction is completed when the transaction layer 2601 of the requesting node confirms the acknowledge packet.
FIG. 45 shows a data flow in a split transaction, which is the other kind of transaction. In FIG. 45, a request packet transmitted from a transaction layer 2601 of a requesting node is received by a transaction layer 2604 of a response node similarly to the unified transaction. The transaction node 2604 of the response node transmits an acknowledge packet, which is pending, in response to the request packet to terminate the transaction temporarily. Thereafter, the transaction node 2604 transmits a response packet indicative of completion at a time when the response to the request previously received request is prepared in the transaction layer 2604 of the response node. When the transaction layer 2601 of the request node confirms the packet and the transaction layer 2604 of the response node confirms the transmitted acknowledge packet, the transaction is completed.
In the IEEE1394 bus, since the above mentioned bus resetting occurs to perform the initialization of the bus every time when a cable is connected or disconnected, the efficiency of bus utilization is lowered. In order to solve this problem, an IEEE1394 bus bridge for dividing bus by using the bus ID is defined by P13934.1 and an example thereof is disclosed in JPH11-220485A.
Since, in the conventional IEEE1394 bus described hereinbefore, all nodes connected to the bus have the right of use of any one of the nodes connected to the IEEE1394 bus, there is a problem that one node can not occupy other nodes.
Further, since, when the IEEE1394 bus is divided by using the IEEE1394 bus bridge, the step from the bus resetting to the construction of topology information is also divided, there is no means for knowing existence of nodes connected to the bus upstream from the IEEE1394 bus bridge.